EV Group launches EVG 850 NanoClean system for ultra-thin chip stacking for advanced packaging

EV Group, a leading supplier of wafer bonding and lithography equipment in the MEMS, nanotechnology, and semiconductor markets, yesterday launched the EVG850 NanoClean layer release system, which is the first product platform to adopt EVG's revolutionary NanoClean technology.

The EVG850 NanoClean system combines infrared lasers with specially formulated inorganic release materials, and can release bonding layers, deposition layers, or growth layers with nanoscale precision from silicon substrates on mature and mass-produced platforms. Therefore, EVG3 NanoClean does not require a glass carrier and can achieve ultra-thin chip stacking for advanced packaging, as well as ultra-thin 3D layer stacking for front-end processing, including advanced logic, memory, and power device formation, to support future 3D integration roadmaps.

The first batch of EVG850 NanoClean systems has been installed at the customer's factory and is currently undergoing nearly twenty product demonstrations with customers and partners at the customer's site and EVG headquarters.

Silicon carriers are beneficial for 3D stacking and backend processing
In 3D integration, glass substrates have become a mature method of constructing device layers through temporary bonding with organic adhesives, using ultraviolet wavelength lasers to dissolve the adhesive and release the device layer, and then permanently bonding it onto the final product wafer. However, it is difficult to process glass substrates using semiconductor wafer fab equipment primarily designed around silicon, and expensive upgrades are required to achieve glass substrate processing. In addition, organic adhesives are usually limited to processing temperatures below 300 ° C, which limits their use in back-end processing.

Adding an inorganic release layer to the silicon carrier can avoid compatibility issues between these temperatures and the glass carrier. In addition, infrared laser induced cutting has nanometer level accuracy and can process extremely thin device wafers without changing the recording process. The subsequent stacking of thin device layers can achieve higher bandwidth interconnection and provide new opportunities for chip design and segmentation of next-generation high-performance devices.

The next generation of transistor nodes requires thin layer transmission technology
At the same time, the transistor roadmap for sub 3 nanometer nodes requires new architectures and design innovations, such as buried power rails, backside power supply networks, complementary field-effect transistors, and 2D atomic channels, all of which require layer transfer of extremely thin materials. The silicon carrier and inorganic release layer support the process cleanliness, material compatibility, and high processing temperature requirements of the front-end manufacturing process. However, so far, the silicon carrier has to be completely removed through grinding, polishing, and etching processes, which results in micrometer level changes on the surface of the working device layer, making this method unsuitable for thin layer stacking at advanced nodes.

Releasable fusion
The EVG850 NanoClean uses infrared laser and inorganic release materials, which can perform laser cutting from silicon charge carriers with nanoscale accuracy in the production environment. This innovative process eliminates the need for glass substrates and organic adhesives, making the transfer of ultra-thin layers compatible with the front-end processes of downstream processes. The high temperature compatibility of EVG850 NanoClean supports the most demanding front-end processing, while the room temperature infrared cutting step ensures the integrity of the device layer and carrier substrate. The layer transfer process also eliminates the need for expensive solvents related to substrate wafer grinding, polishing, and etching.

The EVG850 NanoClean and EVG's industry-leading EVG850 series automatic temporary bonding/debonding and silicon on insulator bonding systems are based on the same platform, featuring a compact design and HVM validated wafer processing system.

Dr. Bernd Thallner, Enterprise R&D Project Manager at EV Group, stated: Since its establishment over 40 years ago, EVG's vision has always been to be the first to explore new technologies and serve the next generation of applications in micro and nano processing technology. Recently, 3D and heterogeneous integration have become key driving factors for improving the performance of next-generation semiconductor devices. This in turn makes wafer bonding a key process for continuing to expand PPACt. Through our new EVG850 NanoClean system, EVG integrates the advantages of temporary bonding and melt bonding into the next generation of semiconductor devices In a multifunctional platform, we support our customers in expanding their future roadmap in advanced packaging and next-generation scaling transistor design and manufacturing.

Source: Laser Net